Contents
1. Introduction ……………………………………………………………………………………………………. 4
2. Design …………………………………………………………………………………………………………… 4
3. Implementation ……………………………………………………………………………………………….. 5
4. Results…………………………………………………………………………………………………………… 6
5. Conclusions ……………………………………………………………………………………………………. 7
4-Bit Synchronous Up Counter 3
List of Figures
Figure 1 – System Design …………………………………………………………………5
Figure 2 – Input Signals and Output Waveforms ………………………………….…….6
4-Bit Synchronous Up Counter 4
1. Introduction
Quartus 2 is a software package produced by Intel, intended for programmable logic
device design. The aim of the assignment is to design a Four-Bit Synchronous Up
Counter using the Quartus 2 software package, aimed at fulfilling the following list of
objectives:
a. To design the schematic diagram of the Four-Bit Synchronous Up Counter using
JK-Flip Flop, intended to count for every rising edge in the input clock signal from
0000 to 1111 before resetting to 0000.
b. To visualize and study the waveform of the input clock signal.
c. To visualize and analyse the waveforms of the output signals: DCBA.
d. To observe the system simulation of the Four-Bit Synchronous Up Counter.
The Assignment helps reveal the modalities of the software package while giving the
student a hands-on experience in using the said software to design digital electronic
circuits of much higher levels of complexity than the current assignment.
2. Design
The given Four-Bit Synchronous up Counter is designed using the JK-Flip Flop. A
synchronous counter is a type of counter wherein all the clock inputs of the flip-flops
are connected to the same external clock signal source, such that the clocking all the
flip-flops occurs simultaneously and the changes in the output of the flip-flops is
synchronized with the clock signal. As against an asynchronous counter wherein
each flip-flop gets a separate external clock signal as a clock input, synchronous
counters reduce propagation delay, cost of the circuit due to reduced components,
etc.
The circuit consists of four JK Flip-Flops, two AND gates, an external Clock signal
and a single Vcc input voltage source. The outputs of the flip-flops are connected to
4-Bit Synchronous Up Counter 5
an LED.
Figure 1: System Design
3. Implementation
The Four-Bit Synchronous Up Counter circuit is constructed in Quartus 2 software
package, with web-version of 12.1, running on a 64-bit configuration. Before
proceeding to any step, it is imperative to create a New Project Wizard in the software.
Follow the following steps to create the same:
a. Project Directory: Any Disk Space
b. Project Name: 4_bitcounter
c. Number of files added: 0
d. Number of user libraries added: 0
e. Device Family Name: Max 2
f. Device: EPM2210F324C3
g. EDA Tools: Altera Model Sim
h. Vcc INT: 3.3 V
i. Junction Temperature Range: 0-85oC
4-Bit Synchronous Up Counter 6
After creating a New Project Wizard, create a new Schematic File and construct the
Four-Bit Synchronous Up Counter according to the Design section mentioned above.
After constructing the circuit, press Ctrl+L to compile the schematic circuit, check for
any error messages thrown during the stage of compilation.
After a successful compilation of the circuit, Pins were assigned to the circuit
(Ctrl+Shift+N), and then Nodes were assigned to the Clock input and the four-bit
output LEDs using the NodeFinder.
Open Altera Model Sim, and load the schematic file made above into the Altera Model
Sim to visualize the output waveforms.
4. Results
The circuit output waveforms is visualized in Altera Model Sim sub-module of the
Quartus 2 software and the variations in the output waveform for the changes in the
input waveform (external clock signal) was observed and noted.
Figure 2 – Input Signals and Output Waveforms
4-Bit Synchronous Up Counter 7
5. Conclusions
A Synchronous counter counts an event for every rising positive edge of the clock
signal, i.e., every time there is a rising edge in the input external clock signal, the flipflop output increases by 1 until 1111 is reached, after which the counter is reset to 0000
on the next rising edge. Because the input of the first flip-flop is connected to logic 1
(HIGH), the flip-flip toggles at every clocking pulse, i.e., the A bit toggles every
clocking pulse.
The toggling of the previous JK-Flip Flop allows for the toggling of the next flip-flop
because of cascade connection between the output of the previous flip-flop and the
input of the current flip-flop.