Contents
1. Introduction ……………………………………………………………………………………………………. 4
2. Design …………………………………………………………………………………………………………… 4
3. Implementation ……………………………………………………………………………………………….. 5
4. Results…………………………………………………………………………………………………………… 7
5. Conclusions ……………………………………………………………………………………………………. 7
6. Appendix A: Source Code (If Applicable)………………………………………………………..8

1. Introduction Quartus 2 is a software package produced by Intel, intended for programmable logic device design. The aim of the assignment is to design a Four-Bit Synchronous Up Counter using the Quartus 2 software package, aimed at fulfilling the following list of objectives: a. To design the schematic diagram of the Four-Bit Synchronous Up Counter using JK-Flip Flop, intended to count for every rising edge in the input clock signal from 0000 to 1111 before resetting to 0000. b. To visualize and study the waveform of the input clock signal. c. To visualize and analyse the waveforms of the output signals: DCBA. d. To observe the system simulation of the Four-Bit Synchronous Up Counter. The Assignment helps reveal the modalities of the software package while giving the student a hands-on experience in using the said software to design digital electronic circuits of much higher levels of complexity than the current assignment. 2. Design The given Four-Bit Synchronous up Counter is designed using the JK-Flip Flop. A synchronous counter is a type of counter wherein all the clock inputs of the flip-flops are connected to the same external clock signal source, such that the clocking all the flip-flops occurs simultaneously and the changes in the output of the flip-flops is synchronized with the clock signal. As against an asynchronous counter wherein each flip-flop gets a separate external clock signal as a clock input, synchronous counters reduce propagation delay, cost of the circuit due to reduced components, etc. The circuit consists of four JK Flip-Flops, two AND gates, an external Clock signal and a single Vcc input voltage source. The outputs of the flip-flops are connected to LED. 4-Bit Synchronous Up Counter 5 Figure 1: System Design 3. Implementation The Implementation phase of the project can be broken down into two distinct parts: a. Quartus II The Four-Bit Synchronous Up Counter circuit is constructed in Quartus 2 software package, with web-version of 12.1, running on a 64-bit configuration. Before proceeding to any step, it is imperative to create a New Project Wizard in the software. Follow the following steps to create the same: a. Project Directory: Any Disk Space b. Project Name: counter-4bit c. Number of files added: 0 d. Number of user libraries added: 0 e. Device Family Name: Max 2 f. Device: EPM240T100C5 g. EDA Tools:  Design entry/ synthesis: () 4-Bit Synchronous Up Counter 6  Simulation: ModelSim (VHDL)  Timing Analysis: None h. Operating Conditions:  Vcc INT: 3.3 V  Junction Temperature Range: 0-85oC After creating a New Project Wizard, create a new Schematic File and construct the Four-Bit Synchronous Up Counter according to the Design section mentioned above. After creating the schematic file of the circuit in Quartus II, follow the path: ‘ProcessingAnalyze Current File’ to analyse the circuit.After analysing the circuit, press Ctrl+L to compile the schematic circuit, check for any error messages thrown during the stage of compilation. After a successful compilation of the circuit, Pins were assigned to the circuit by pressing Ctrl+Shift+N or by following the path ‘AssignmentsPin Planner’. The Pin Planner tool is used to assign the input and output ports of the circuit to the respective pins of the device for which the simulation is being run, i.e. EPM240T100C5 in this case. b. Altera ModelSim Open Altera Model Sim, version 10.1. Go to ‘FileChange Directory’ to change the directory of the project to the folder in which the Quartus II file is saved (current project directory path); and then follow path ‘FileNewLibrary’ to create a new library with any name of choice for the given project (do so within the same folder as that of the changed directory). The newly created library will appear in the Library window, wherein single-click on the new library and click ‘CompileCompile’ to add the ‘.vho’ file stored in the ‘ModelSim’ folder of the directory (SimulationModelSim.vho) and click ‘Compile’. 4-Bit Synchronous Up Counter 7 Go to the Library window and click on the newly created library in order to expand it, wherein the newly compiled file is found; the file is double-clicked to open the simulation window wherein click on ‘Run’ to simulate the project and observe the waveform’ 4. Results The circuit output waveforms is visualized in Altera Model Sim and the variations in the output waveform for the changes in the input waveform (external clock signal) was observed and noted. Starting from the top: Green (Vcc), Red (Clock), Blue (A), Yellow (B), Pink (C) and Brown (D). The D bit is the MSB of the counting sequence. It can be observed that the A bit switches states over one complete period of the clocking signal or for every rising edge of the clocking signal. Figure 2 – Input Signals and Output Waveforms 5. Conclusions A Synchronous counter counts an event for every rising positive edge of the clock 4-Bit Synchronous Up Counter 8 signal, i.e., every time there is a rising edge in the input external clock signal, the flipflop output increases by 1 until 1111 is reached, after which the counter is reset to 0000 on the next rising edge. Because the input of the first flip-flop is connected to logic 1 (HIGH), the flip-flip toggles at every clocking pulse, i.e., the A bit toggles every clocking pulse. The toggling of the previous JK-Flip Flop allows for the toggling of the next flip-flop because of cascade connection between the output of the previous flip-flop and the input of the current flip-flop. 6. Appendix A: Source Code (If Applicable) — Copyright (C) 1991-2012 Altera Corporation — Your use of Altera Corporation’s design tools, logic functions — and other software and tools, and its AMPP partner logic — functions, and any output files from any of the foregoing — (including device programming or simulation files), and any — associated documentation or information are expressly subject — to the terms and conditions of the Altera Program License — Subscription Agreement, Altera MegaCore Function License — Agreement, or other applicable license agreement, including, — without limitation, that your use is for the sole purpose of — programming logic devices manufactured by Altera and sold by — Altera or its authorized distributors. Please refer to the — applicable agreement for further details. — VENDOR “Altera” — PROGRAM “Quartus II 64-Bit” 4-Bit Synchronous Up Counter 9 — VERSION “Version 12.1 Build 177 11/07/2012 SJ Web Edition” — DATE “01/01/2020 05:00:29” — Device: Altera EPM240T100C5 Package TQFP100 — This VHDL file should be used for ModelSim (VHDL) only LIBRARY IEEE; LIBRARY MAXII; USE IEEE.STD_LOGIC_1164.ALL; USE MAXII.MAXII_COMPONENTS.ALL; ENTITY counter_4bit IS PORT ( A : OUT std_logic; Clock : IN std_logic; B : OUT std_logic; C : OUT std_logic; D : OUT std_logic ); END counter_4bit; — Design Ports Information — Clock => Location: PIN_14, I/O Standard: 3.3-V LVTTL, Current Strength: Default — A => Location: PIN_92, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA 4-Bit Synchronous Up Counter 10 — B => Location: PIN_95, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA — C => Location: PIN_96, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA — D => Location: PIN_97, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA ARCHITECTURE structure OF counter_4bit IS SIGNAL gnd : std_logic := ‘0’; SIGNAL vcc : std_logic := ‘1’; SIGNAL unknown : std_logic := ‘X’; SIGNAL devoe : std_logic := ‘1’; SIGNAL devclrn : std_logic := ‘1’; SIGNAL devpor : std_logic := ‘1’; SIGNAL ww_devoe : std_logic; SIGNAL ww_devclrn : std_logic; SIGNAL ww_devpor : std_logic; SIGNAL ww_A : std_logic; SIGNAL ww_Clock : std_logic; SIGNAL ww_B : std_logic; SIGNAL ww_C : std_logic; SIGNAL ww_D : std_logic; SIGNAL Clock~combout : std_logic; SIGNAL inst~regout : std_logic; 4-Bit Synchronous Up Counter 11 SIGNAL inst1~regout : std_logic; SIGNAL inst2~regout : std_logic; SIGNAL inst3~regout : std_logic; BEGIN A <= ww_A; ww_Clock <= Clock; B <= ww_B; C <= ww_C; D <= ww_D; ww_devoe <= devoe; ww_devclrn <= devclrn; ww_devpor <= devpor; — Location: PIN_14, I/O Standard: 3.3-V LVTTL, Current Strength: Default Clock~I : maxii_io — pragma translate_off GENERIC MAP ( operation_mode => “input”) — pragma translate_on PORT MAP ( oe => GND, padio => ww_Clock, combout => Clock~combout); — Location: LC_X3_Y4_N6 4-Bit Synchronous Up Counter 12 inst : maxii_lcell — Equation(s): — inst~regout = DFFEAS((((!inst~regout))), GLOBAL(Clock~combout), VCC, , , , , , ) — pragma translate_off GENERIC MAP ( lut_mask => “0f0f”, operation_mode => “normal”, output_mode => “reg_only”, register_cascade_mode => “off”, sum_lutc_input => “datac”, synch_mode => “off”) — pragma translate_on PORT MAP ( clk => Clock~combout, datac => inst~regout, aclr => GND, devclrn => ww_devclrn, devpor => ww_devpor, regout => inst~regout); — Location: LC_X3_Y4_N3 inst1 : maxii_lcell — Equation(s): 4-Bit Synchronous Up Counter 13 — inst1~regout = DFFEAS(((inst~regout $ (inst1~regout))), GLOBAL(Clock~combout), VCC, , , , , , ) — pragma translate_off GENERIC MAP ( lut_mask => “0ff0”, operation_mode => “normal”, output_mode => “reg_only”, register_cascade_mode => “off”, sum_lutc_input => “datac”, synch_mode => “off”) — pragma translate_on PORT MAP ( clk => Clock~combout, datac => inst~regout, datad => inst1~regout, aclr => GND, devclrn => ww_devclrn, devpor => ww_devpor, regout => inst1~regout); — Location: LC_X3_Y4_N9 inst2 : maxii_lcell — Equation(s): 4-Bit Synchronous Up Counter 14 — inst2~regout = DFFEAS((inst2~regout $ (((inst~regout & inst1~regout)))), GLOBAL(Clock~combout), VCC, , , , , , ) — pragma translate_off GENERIC MAP ( lut_mask => “3ccc”, operation_mode => “normal”, output_mode => “reg_only”, register_cascade_mode => “off”, sum_lutc_input => “datac”, synch_mode => “off”) — pragma translate_on PORT MAP ( clk => Clock~combout, datab => inst2~regout, datac => inst~regout, datad => inst1~regout, aclr => GND, devclrn => ww_devclrn, devpor => ww_devpor, regout => inst2~regout); — Location: LC_X3_Y4_N0 inst3 : maxii_lcell — Equation(s): 4-Bit Synchronous Up Counter 15 — inst3~regout = DFFEAS(inst3~regout $ (((inst1~regout & (inst~regout & inst2~regout)))), GLOBAL(Clock~combout), VCC, , , , , , ) — pragma translate_off GENERIC MAP ( lut_mask => “6ccc”, operation_mode => “normal”, output_mode => “reg_only”, register_cascade_mode => “off”, sum_lutc_input => “datac”, synch_mode => “off”) — pragma translate_on PORT MAP ( clk => Clock~combout, dataa => inst1~regout, datab => inst3~regout, datac => inst~regout, datad => inst2~regout, aclr => GND, devclrn => ww_devclrn, devpor => ww_devpor, regout => inst3~regout); — Location: PIN_92, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA A~I : maxii_io 4-Bit Synchronous Up Counter 16 — pragma translate_off GENERIC MAP ( operation_mode => “output”) — pragma translate_on PORT MAP ( datain => inst~regout, oe => VCC, padio => ww_A); — Location: PIN_95, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA B~I : maxii_io — pragma translate_off GENERIC MAP ( operation_mode => “output”) — pragma translate_on PORT MAP ( datain => inst1~regout, oe => VCC, padio => ww_B); — Location: PIN_96, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA C~I : maxii_io — pragma translate_off GENERIC MAP ( operation_mode => “output”) 4-Bit Synchronous Up Counter 17 — pragma translate_on PORT MAP ( datain => inst2~regout, oe => VCC, padio => ww_C); — Location: PIN_97, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA D~I : maxii_io — pragma translate_off GENERIC MAP ( operation_mode => “output”) — pragma translate_on PORT MAP ( datain => inst3~regout, oe => VCC, padio => ww_D); END structure;