Electronic engineering

Provide detailed answers to the following:
1. Perform the following conversions:
a. 456.14 in Octal to Decimal
b. 1000.7 in Decimal to Hexadecimal
c. A5B.0C.in Hexadecimal to Octal
d. 11011.011 in Binary to Octal

2. Simplify the following:
a. xyz + x’y + xyz’
b. ABC + A’B + ABC’
c. (x + y)’ (x’ + y’)

3. List the truth table of the following functions. Also draw the logic diagram (gate implementation of the following functions)
a. F = xy + xy’ + y’z
b. Y = (A + B) (C’ + D)
4. Write the canonical sum of products and canonical product of sums for the following functions:
a. F = ΣX,Y,Z(0,3)
b. F = ΠA,B,C(1,2,4)

5. Write Verilog code to describe the following functions:
a. f1 = x1x3’ + x2x3’ + x3’x4’ + x1x2 +x1x4’
b. f2 = (x1 + x3’) . (x1 + x2 + x4’) . (x2 + x3’ + x4’)

6. A given system has 3 sensors that can produce an output of 0 or 1. The system operates properly when exactly one of the sensors has its output equal to 1. An alarm must be raised when two or more sensors have the output of 1. Design the simplest circuit that can be used to raise the alarm. Use K-MAP for the simplest circuit.
1. Problem Statement and Analysis
For this laboratory, you will use the two-way light controller circuit shown in Figure 1. The circuit can be used to control a single light from either of the two switches, x1 and x2, where a closed switch corresponds to the logic value 1. The truth table for the circuit is also given in the figure. Note: this is only the Exclusive-OR function of the inputs x1 and x2; you will need to specify it using the gates shown.
The required circuit is described by the Verilog code in Figure 2. This code can be typed into a file by using any text editor that stores ASCII files, or by using the Quartus II text editing facilities. While the file can be given any name, designers generally use the same name as that of the top-level Verilog module. The file name must include the extension v, which indicates a Verilog file. Accordingly, you will use the name light v.
module light (x1, x2, f);
input x1, x2;
output f;
assign f = (x1&∼x2) | (∼x1& x2);
end module

Figure 2: Verilog Code for the circuit in Figure 1

[Note: ~ sign represents inverse in Verilog. This is located below the Esc key on most keyboards.]

On the basis of the above explanation, complete the following:
Step 1 – Downloading and Installing Quartus II
Download and install the latest version of the software by following the step-by-step process below:
1. Go to the following URL:
You must create an account by entering your email address. You will also be asked to enter some personal information to complete the registration process.
2. After creating an account, click on the “Download Center” at the top of the page.
3. On the next page, click on the “Free Web Package” button.
4. You will download the latest version of the software: Quartus II Web Edition v14.1 (This is the default version, so there is no need to change it). You must select the “Operating System” and “Download Method”. Choose “Direct Download” as your “Download Method”.
5. There are three options for downloading the software. If you want to download the complete package, which is 4.5 GB, you must select “Combined Files”. However, for the purpose of this course, there is no need to install all files. Therefore, you can select the “Individual Files” option and download the following files only, which is 2.5 GB in total:
Note: Remember to download all the files into a same directory.
a. Quartus II Software (includes Nios II EDS)
b. ModelSim-Altera Edition (includes Starter Edition)
c. MAX II, MAX V, MAX 3000, MAX 7000 device support
d. Quartus II Help
6. After downloading the required files, you are now ready to install the software. To do so, run the QuartusSetupWeb- file and follow the installation process. There is no need to modify anything in the process.
7. Once the installation is complete, the software will be launched automatically.

Step 2 – Creating and Compiling the Project with Quatrus II Verilog
Read sections 3 through 6 of the file Quatrus_II_Introduction.pdf. Follow the steps in these sections and enter the Verilog code in Figure 2 to Quatrus II program.

Step 3 – Simulating the Project with Quatrus II Verilog
Read section 8 of the file Quatrus_II_Introduction.pdf. Follow the steps in this section. Simulate the Verilog code and generate the output waveform.

Step 4 – Checking the Simulation
Check your simulation and make sure that your simulation satisfies the design requirements (the Truth Table in Figure 1).

Step 5 – Writing the Lab report
Write the laboratory report using the laboratory report format.

Step 6 – Submitting the Report
Submit your report by the due date.
Use the American Psychological Association (APA) style (6th edition) for writing your assignment.

Compose your work using a word processor (or other software as appropriate) and save it frequently to your computer. Be sure to check your work and correct any spelling or grammatical errors before you upload it. When you are ready to submit your work, click “Browse My Computer” and find your file. Once you have located your file, click “Open” and, if successful, the file name will appear under the Attached files heading. Scroll to the bottom of the page and click “Submit.”

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